1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device, and particularly to mask type and floating gate electrode type non-volatile semiconductor memory devices and a method for driving the same.
2. Description of the Related Art
In recent years, a non-volatile semiconductor memory device which operates at a low voltage and a high speed has been utilized. In order to widely provide such a non-volatile semiconductor memory device, there is a demand for a non-volatile semiconductor memory device capable of operating at a low voltage and a high speed, and a method for driving the same.
Hereinafter, a conventional non-volatile semiconductor memory device 500 will be described with reference to FIGS. 15, 16, and 17.
The non-volatile semiconductor memory device 500 has a NOR type memory cell array structure, in which a plurality of memory cells are connected in parallel to bit lines.
FIG. 15 is a schematic diagram showing a structure of a memory cell array of the non-volatile semiconductor memory device 500.
The non-volatile semiconductor memory device 500 shown in FIG. 15 includes memory cells M11 through M44 composed of MOS transistors, word lines WL1 through WL4, source lines SL1 through SL3, and bit lines BL1 through BL4.
In the non-volatile semiconductor memory device 500, as shown in FIG. 15, a gate of the memory cell M24 is connected to the word line WL2, a source of the memory cell M24 is connected to the source line SL2, and a drain of the memory cell M24 is connected to the bit line BL4. In the non-volatile semiconductor memory device 500, the memory cells M21 through M24 and the memory cells M31 through M34 share the source line SL2. The memory cells M11 through M14 and the memory cells (not shown) opposed thereto share the source line SL1. This is also applicable to the source line SL3.
FIG. 16 is a schematic plan view showing a layout pattern of the non-volatile semiconductor memory device 500 shown in FIG. 15.
As shown in FIG. 16, the non-volatile semiconductor memory device 500 includes isolation regions 5 and bit line contacts 6.
Hereinafter, a write method and a read method of the non-volatile semiconductor memory device 500 will be described with reference to FIG. 17.
FIG. 17 shows a threshold voltage distribution diagram of memory cells in the non-volatile semiconductor memory device 500. In FIG. 17, the abscissa represents a threshold voltage V.sub.TM of the memory cells, and the ordinate represents the number of memory cells.
It is assumed herein that the non-volatile semiconductor memory device 500 is a mask ROM composed of N-type MOS transistors having two different threshold voltages.
An erase state ("E" state in FIG. 17) refers to that N-type MOS transistors are set at a threshold voltage (lower threshold voltage) of about 1 volt, in which the N-type MOS transistors are in an enhancement state. The erase state is controlled by ion implantation to the channel portions of memory cells in the entire memory array.
A write state ("W" state in FIG. 17) refers to that ions are additionally implanted only to the channels of selected N-type MOS transistors, whereby the selected N-type MOS transistors are set at a threshold voltage (higher threshold voltage) of about 4 volts, which is higher than a supply voltage V.sub.DD and in which the N-type MOS transistors are in an enhancement state.
Hereinafter, a read method of the non-volatile semiconductor memory device 500 will be described with reference to FIG. 15.
In the case where the memory cell M24 surrounded by a broken line in FIG. 15 is selected, an electric potential of a semiconductor substrate is set at a ground voltage (0 volts), the word line WL2 is set at about 3 volts, and the bit line BL4 is set at about 1 volt, respectively. Furthermore, the other word lines WL1, WL3, and WL4, the source lines SL1 through SL3, and the other bit lines BL1, BL2, and BL3 are set at about 0 volts or set to be an OPEN state. The semiconductor substrate on which a memory array is arranged in FIG. 15 is fixed at a ground voltage, based on which a voltage is applied to the other portions.
If the memory cell M24 is in an erase state, the threshold voltage thereof is set at about 0.5 volts. Therefore, the memory cell M24 turns on, and a current for reading information from the memory cell flows through the bit line BL4. On the other hand, if the memory cell M24 is in a write state, the threshold voltage thereof is set at about 4 volts. Therefore, the memory cell M24 turns off, and a current for reading information from the memory cell does not flow through the bit line BL4. The amount of the current is detected by a sense amplifier, and a read operation is performed.
As described above, the information stored in the selected memory cell M24 is read by using the amount of the current for reading the information from the memory cell which flows through the memory cell M24. Therefore, it is required that currents flowing from the non-selected memory cells M14, M34, and M44 connected to the bit line BL4 to which the memory cell M24 is also connected are set at about 0. In order to do this, the threshold voltages of these non-selected memory cells are required to be set at about 0.5 volts or higher.
However, in the non-volatile semiconductor memory device 500 and the method for rewriting information using the same, the threshold voltage of a memory cell in an erase state (i.e., the lower threshold voltage) is set at about 0.5 volts or higher. Therefore, if the non-volatile semiconductor memory device 500 is operated at a low voltage (lower supply voltage), the amount of a current for reading information from the memory cell in an erase state (ON state) becomes small during reading, making it difficult to read information at a high speed.